The subject matter relates to a semiconductor device, and more particularly, to an apparatus and a method for generating multi-phase clocks, which is capable of reducing phase differences between the multi-phase clocks caused by a duty error.
In a semiconductor device such as a double data rate synchronous dynamic random access memory (DDR SDRAM), its operation speed gradually increases, its chip size gradually decrease, and its operation voltage gradually decreases. Furthermore, the number of multi-phase clocks (MCLK) used in the semiconductor device are gradually increased. The multi-phase clocks are a plurality of clocks separated sequentially by a predetermined phase difference.
FIG. 1 is a block diagram of a conventional apparatus for generating multi-phase clocks.
Referring to FIG. 1, the conventional apparatus for generating multi-phase clocks includes a clock delay 110, a first control buffer 120, a second control buffer 130, a clock buffer 160, a phase detector 140, and a control voltage signal generator 150.
The clock delay 110 includes a first clock delay circuit 112, a second clock delay circuit 114, a third clock delay circuit 116 and a fourth clock delay circuit 118. Each of the clock delay circuits 112, 114, 116 and 118 delays a clock input thereto by a delay time corresponding to a control voltage signal V_CTR. In more detail, the first clock delay circuit 112 delays first clocks CLK0 and /CLK0 input thereto by a predetermined delay time to output second clocks CLK45 and /CLK45. The second clock delay circuit 114 delays the second clocks CLK45 and /CLK45 to output third clocks CLK90 and /CLK90. The third clock delay circuit 116 delays the third clocks CLK90 and /CLK90 to output fourth clocks CLK135 and /CLK135. The fourth clock delay circuit 118 delays the fourth clocks CLK135 and /CLK135 to output fifth clocks CLK180 and /CLK180.
The clock /CLK0 is an inverted signal of the clock CLK0. Hereinafter, the clock CLK0 is referred to as a “first positive clock” and the clock /CLK0 is referred to as a “first negative clock”, which is applied in the cases of the second clocks CLK45 and /CLK45, the third clocks CLK90 and /CLK90, the fourth clocks CLK135 and /CLK135, and the fifth clocks CLK180 and /CLK180.
A first control buffer 120 buffers the first clocks CLK0 and /CLK0 to output a first input signal IN0 corresponding to the first positive clock CLK0. A second control buffer 130 buffers the fifth clocks CLK180 and /CLK180 to output a second input signal /IN180 corresponding to the fifth negative clock /CLK180.
The phase detector 140 detects a phase of the second input signal /IN180 in comparison to that of the first input signal IN0 to generate an up detection signal DET_UP or a down detection signal DET_DOWN according to the detection results. For example, if a rising edge of the second input signal /IN180 leads a rising edge of the first input signal IN0, the up detection signal DET_UP is generated to increase the delay time of the clock delay circuits 112, 114, 116 and 118. If the rising edge of the second input signal /IN180 lags behind the rising edge of the first input signal IN0, the down detection signal DET_DOWN is generated to decrease the delay time of the clock delay circuits 112, 114, 116 and 118.
The control voltage signal generator 150 generates a control voltage signal V_CTR having a voltage level corresponding to the up detection signal DET_UP or the down detection signal DET_DOWN. For example, the voltage level of the control voltage signal V_CTR decreases in response to the up detection signal DET_UP, but increases in response to the down detection signal DET_DOWN.
The control voltage signal V_CTR controls the delay time of the clock delay circuits 112, 114, 116 and 118. For example, as the voltage level of the control voltage signal V_CTR decreases, the clock delay circuits 112, 114, 116 and 118 increase the delay time thereof. On the contrary, as the voltage level of the control voltage signal V_CTR increases, the clock delay circuits 112, 114, 116 and 118 decrease the delay time thereof.
By repeatedly adjusting the delay time of the clock delay circuits 112, 114, 116 and 118, rising edges of the first positive clock CLK0 and the fifth negative clock /CLK180 can coincide with each other, which is called “locking.”
If a duty ratio of the first clocks CLK0 and /CLK0 is 50:50, the clock delay 110 may delay the first positive clock CLK0 by 180° after the locking for securing a delay time of the fifth negative clock/CLK180.
The first to fourth clock delay cells 112, 114, 116 and 118 output second clocks CLK45 and /CLK45, third clocks CLK90 and /CLK90, fourth clocks CLK135 and /CLK135 and fifth clocks CLK180 and /CLK180 to the clock buffer 160, respectively. The clock buffer 160 including a plurality of clock buffer circuits 162 to 169 generates a plurality of multi-phase clocks MCLK45, MCLK90, MCLK135, MCLK180, MCLK225, MCLK270, MCLK315 and MCLK0 separated sequentially by a phase difference of 45°.
The first clock buffer circuit 162 receives the second clocks CLK45 and /CLK45 to generate a multi-phase clock MCLK45 having a phase difference of 45° with the first clocks CLK0 and /CLK0. The second clock buffer circuit 163 receives the second clocks /CLK45 and CLK45 to generate a multi-phase clock MCLK225 having a phase difference of 225° with the first clocks CLK0 and /CLK0. The multi-phase clock MCLK45 has a phase corresponding to that of the second positive clock CLK45, whereas the multi-phase clock MCLK225 has a phase corresponding to that of the second negative clock /CLK45.
The third and fourth clock buffer circuits 164 and 165 may receive the third clocks CLK90 and /CLK90 to generate a multi-phase clock MCLK90 having a phase difference of 90° and a multi-phase clock MCLK270 having a phase difference of 270° with the first clocks CLK0 and /CLK0. The fifth and sixth clock buffer circuits 166 and 167 may receive the fourth clocks CLK135 and /CLK135 to generate a multi-phase clock MCLK135 having a phase difference of 135° and a multi-phase clock MCLK315 having a phase difference of 315° with the first clocks CLK0 and /CLK0. The seventh and eighth clock buffer circuits 168 and 169 may receive the fifth clocks CLK180 and /CLK180 to generate a multi-phase clock MCLK180 having a phase difference of 180° and a multi-phase clock MCLK0 having a phase difference of 0° with the first clocks CLK0 and /CLK0.
Such multi-phase clocks MCLK45, MCLK90, MCLK135, MCLK180, MCLK225, MCLK270, MCLK315 and MCLK0 should be spaced sequentially at an interval of 45° to divide a cycle of the first clocks CLK0 and /CLK0 into eight equal parts. However, if the duty ratio of the first clocks CLK0 and /CLK0 is changed, the desired interval cannot be maintained. This will be described later in more detail with reference to FIG. 2.
FIG. 2 is an operation timing diagram of the conventional apparatus for generating multi-phase clocks shown in FIG. 1. For convenience, the first input signal IN0 will be regarded to be identical to the first positive clock CLK0 and the second input signal /IN180 will be regarded to be identical to the fifth negative clock /CLK180. Further, it will be assumed that a cycle of the first positive clock CLK0 is “Tcyc” and a duty ratio of the first positive clock CLK0 is changed by Δt such that a logic low portion of the first positive clock CLK0 has a width of Tcyc/2±Δt.
Referring to FIGS. 1 and 2, the fifth clocks CLK180 and /CLK180 are generated by delaying the first clocks CLK0 and /CLK0 by a basic delay time at the clock delay 110. Thereafter, the above described locking operation is performed to gradually shift the fifth clocks CLK180 and /CLK180. The locking operation is repeated until the rising edge of the fifth negative clock /CLK180 coincides with the rising edge of the first positive clock CLK0.
When the locking operation is completed, a delay time of the clock delay 110 becomes Tcyc/2±Δt. Accordingly, a delay time of each of the clock delay circuits 112, 114, 116 and 118 becomes a quarter of Tcyc/2±Δt, and therefore a phase error of Δt/4 occurs between each sequential pair of the multi-phase clocks MCLK45, MCLK90, MCLK135, MCLK180, MCLK225, MCLK270, MCLK315 and MCLK0. Such phase errors may impair credibility of the multi-phase clocks, which will become more serious as the frequency of the clocks increases.